application note 1096 dec. 2012 rev. 1. 0 bcd semiconductor manufacturing limited 1 high voltage green mode pwm controller ap3105na/nv/nl/nr prepared by wu qikun system engineering dept. 1. introduction the ap3105nx is a low start-up current, current mode pwm controller with green-mode power-saving operation. different from ap3103, ap3105nx?s pwm switching frequency at normal operation is fixed at 65khz dithering with a narrow range. the difference between ap3103 and ap3105nx is shown in table 1. the dithering of frequency will improve emi feature. when the load decreases, the frequency will reduce and when at a very low load, the ic will enter the ?burst mode? to minimize switching loss. a minimum 20khz frequency switching is to avoid the audible noise as well as to reduce the standby loss. a so-called vcc maintain mode is applied under light load to realize a stable output and to reduce the loss on the start-up resistor. the standby power of the system using ap3105nx can be reduced to 60mw at 230v input. ap3103 ap3105nx frequency adjustable fixed at 65khz v fb resistor 4.5k ? 10k ? standby performance better best external protection na by ?ctrl? pin vcc ovp auto-recoverable latch /auto-recoverable olp & focp auto-recoverable latch /auto-recoverable table 1. the difference between ap3103/ap3105nx the ap3105nx integrates a lot of functions such as the lead edge blanking (leb) of the current sensing, internal slope compensation and several protection features which include cycl e-by-cycle current limit (ocp), fast ocp (focp), vcc over voltage protection, otp, olp protection. the ?ctrl? pin is designed for customers to add external protection functions such as ovp and otp. the ap3105nx is specially designed for off-line ac-dc power supply, such as lcd monitors, notebook adapters and battery charger applications. it can offer the designers a cost-effective solution while keeping versatile protection features. the ic uses the sot-23-6 package type to realize its compact size. this application note includes detailed explanation of the ic?s major functions, some considerations about the pcb layout, and methods for reducing the standby power loss, and finally presents a demo design of a 12v 2a adaptor. 2. function description 2.1 ctrl pin for some applications, the system requires external programmable protection function. the ctrl pin has two kinds of modes to trigger the protection: high level trigger and low level trigger. the low threshold voltage is 0.5v and high threshold voltage is 2.5v. when the ctrl pin voltage is lower than 0.5v or higher than 2.5v, latch or auto-restart protection will be triggered (different versions of ap3105nx offer different protection combinations, which are shown in table 2). version vcc ovp olp& focp ctrl (low) ctrl (high) ap3105na auto- recoverable auto- recoverable latch auto- recoverable ap3105nv latch auto- recoverable latch latch ap3105nl latch latch latch latch AP3105NR auto- recoverable auto- recoverable auto- recoverable latch table 2. version classification of ap3105nx ctrl pin voltage maintains 1.6v if the pin is floating, so leave ctrl pin open if the designer does not need this function. once the latch protection is triggered, the bulk capacito r will provide the energy to the ic through start-up resistor to ensure the ic disable the output signal (latch mode). this mode will not be released until the ac input is shut off. therefore, the de-latch time is mainly depending on the value of hv startup bul k capacitor. if the system needs a short de-latch time, it is better for the startup resistor to take power from the point before the rectifier bridge. typical application of ctrl pin is shown in figure 1. note: 1. the sink current to the ctrl pin should be lower
application note 1096 dec. 2012 rev. 1. 0 bcd semiconductor manufacturing limited 2 than 5ma by selecting a proper pull up resistor. 2. if the designer needs to apply a bypass capacitor on ctrl pin, the capacitor should not be more than 1nf. ovp and otp ovp otp figure 1. ctrl pin application 2.2 difference of ap3105&ap3105nx table 3 shows the difference between ap3105&ap3105nx. table 3. ap3105 vs. ap3105nx 2.3 longer olp delay time for capacitive load a capacitive load needs more power to be charged at start-up time. one solution is to enlarge the ocp point and keep the same start-up time, otherwise it will trigger olp protection mode. another solution is to extend the ocp delay time, which can simplify the transformer design since it is no need to rise the ocp point. thus ap3105nx makes the olp delay time longer to 100ms at st art-up state and 64ms at operating mode. if fb pin?s value is over 4v for 64ms at operating state or for 100ms at start-up, ic will enter olp mode to limit the input power. figure 2 and figure 3 show the startup state with different olp delay time under capacitive load. a shorter delay time may trigger olp under capacitive load while a longer olp delay time resulting start-up succeed. figure 2. shorter olp delay time figure 3. longer olp delay time 2.4 adjusting the prim ary peak current at start-up ap3105nx makes the primary peak current adjustable to limit the v ds crossing mosfet at start-up. an 85 a dc current source is added on sense pin, generating a dc voltage difference between sense pin and v cs , which makes the v cs equal to 0.95v to 85 a*r f (as shown in figure 5). as a result, mosfet?s peak current is limited at start up time, resulting a lower v ds crossing mosfet. this current source will be taken off after 37ms and not be effective under normal operating mode (as shown in figure 4). r f cannot be too large that makes the peak current too small and leads start-up fail at low line input. a proper value of r f is 680 to 2.5k . figure 4. current source at sense pin ap3105 ap3105nx olp delay time 48ms@start-up 32ms@normal operating 100ms@start-up 64ms@normal operating v cs adjustable @ start-up na adjustable
application note 1096 dec. 2012 rev. 1. 0 bcd semiconductor manufacturing limited 3 figure 5. start-up timing of ap3105nx 2.5 fast ocp function when the load is short-circ uited, the power converter can be protected by olp protection. but if the output filter inductor and the secondary schottky are short-circuited, the transformer will be immediately saturated resulting in the breakdown of the mosfet due to high voltage stress. the ap3105nx bears built-in fast ocp function to alleviate the saturation of the transformer and redu ce the voltage stress of mosfet. the focp positio n and focp waveform are shown in figure 7 and figure 8. when the secondary schottky and the output filter inductor is short-circuited, the power converter can trigger latch or auto-restart immediately within several switching cycles with fast ocp. the focp threshold on sense pin is 1.8v. in some applications, high spike voltage appears on the rise edge of the sense pin waveform due to a large transformer primary winding?s parasitic capacitor or an irrational pcb layout , which may exceed the 1.8v thres hold and trigger focp protection by error (as shown in figure 6). to avoid this result, a rc filter is added on sense pin. the recommended resistor value of filter is over 680 when the capacitor is 220pf. figure 6. sense pin rc filter fast ocp figure 7. focp position diode shorten vcc fb figure 8. focp waveform 2.6 vcc maintain mode under load transient condition(heavy load to light load), v fb will drop to lower than 1.4v, thus the pwm drive signal will be stopped, and there is no more energy transferred due to no switching. therefore, the ic supply voltage (vcc) may drop to the uvlo (off) threshold and the system may enter the unexpected restart mode (as shown in figure 9). figure 9. load transient without vcc maintain to avoid this situation, the ap3105nx holds a so-called vcc maintain mode which can supply energy to vcc when vcc decreases to a setting threshold (10.1v), the vcc maintain comparator will
application note 1096 dec. 2012 rev. 1. 0 bcd semiconductor manufacturing limited 4 output a driver signal to make the system switch and provide a proper energy to vcc pin. when vcc increases to 10.6v, the gate signal will be stopped (as shown in figure 10). figure 10. load transient with vcc maintain the vcc maintain function will benefit dynamic transition (full load to light load). it can simplify system loop design. also this mode is designed for reducing startup resistor loss and it will achieve a better standby performance with low value vcc capacitor and larger startup resistor. to avoid the vcc maintain mode triggering in normal operating condition, it is suggested to design the vcc value higher than vcc maintain threshold under minimum load condition(usually at no load). the unexpected processing of vcc maintain mode under no load is shown in figure 11. figure 11. vcc maintain mode triggered @no load 2.7 surge immunity enhanced solutions in some applications, a strict surge test specification is required. for instance, common mode surge is over 6kv. when a large surge voltage is added across the primary and secondary sides of the system, the general ground may be raised higher, thus a current will be thrown out from some pins and damage the internal circuit. if ctrl pin is not floating, r2 is recommended 100k to 200k for eliminating the abnormal current. also r1 is suggested 300 at least and over 1k if it is needed to pass 6kv cm spec. figure 12. surge immunity circuits 2.8 mosfet driver circuit a mosfet consists of many small mosfet cells. for these cells have different distances from the gate pin, insufficiency turn on/off speed will cause partial over-heating of the mosfet and lower efficiency. for system which is over 36w, driver circuit with a push-pull as shown in figure 13 (a) is recommended or at least using figure 13 (b) with a single pull-down transistor. figure 13 (c) can be applied in system that is less than 36w. (a) (b) fb sense vcc gate gnd ctrl 5 6 4 2 1 c ap3105nx r1 r2 3
application note 1096 dec. 2012 rev. 1. 0 bcd semiconductor manufacturing limited 5 (c) figure 13. driver circuit 2.9 start-up circuit a usual applied start-up circuit takes start-up current from bus cap (as shown in figure 14 (b)), but the de-latch time of some protection mode when ac turns off will be long for the bus cap still charges the vcc cap. another start up circuit (as shown in figure 14 (a)) is connected ahead of bridge rectifier. it could reset latch mode protection quickly for vcc cap have a single larger discharge current. the de-latch time is equal to: c vcc is the vcc cap?s value, i delatch is the current that the ic consumed under protection mode. is the error of uvlo threshold and de-latch threshold. thus, a shorter de-latch time needs a smaller vcc cap value. (a) (b) figure 14. start-up circuit 3. standby power loss reduction some methods are recommended here for reducing the standby power loss. 3.1 x-capacitor and x-resistor a good quality x-capacitor will be helpful to save the standby power, and a low value x-cap could also decrease the x-cap loss. acco rding to iec 60950, for the x-cap exceeding 0.1 f, the voltage will be decayed to 37% of its or iginal value during an interval equal to one constant, and after calculating, the rc value is determined by the formula r c<1 . therefore, for a low valu e x-cap, a higher value x-resistor could be used, and the losses on x-resistor will be reduced. 3.2 current sampling resistor the value of current sampli ng resistor could affect the standby power. a lower value cs resistor is good for low standby power. but it also has effects on the olp result: a lower value cs resistor will make a larger olp point. 3.3 ?sense? pin rc value the value of sense pin rc could also affect the standby power. a larger value of rc can make the i peak sense signal and the voltage on fb pin smaller. a smaller voltage on fb pin will result in a lower operating frequency. it is good for achieving low standby power, but it will also make the olp point larger. 3.4 the output voltage dividing resistor the value of output voltage dividing resistor should be as high as possible, but the maximum value of the resistor connected to gnd (r17 in figure 18) should not exceed 15k ? . 3.5 primary rcd clamp circuit to get a better standby pow er, the rcd clamp circuit could be replaced by a transient voltage suppressor (tvs) and a diode (figure 15). the advantage of the tvs clamp is that it only conducts when necessary and it is independent of the switching frequency. compared to a rcd clamp, it reduces no-load power but increases costs and emi. besides, a lower value of rc is contributed to standby power, while the voltage stress on mosfet should be in the spec. a v c i c t vcc delatch vcc delatch 6 . 13 3 . 3 = =
application note 1096 dec. 2012 rev. 1. 0 bcd semiconductor manufacturing limited 6 figure 15. clamp circuit with tvs 4. sense pin rc filter chosen principle table 4 shows the effects with different rc value on sense pin. a proper value of r f is 680 ? to 2.5k ? while the c f value is 33pf to 330pf. figure 16 shows the results of ocp line regulation with different rc value. standby loss ocp line regulation focp trigger v ds & i peak @startup larger r*c less worse not easily lower r*c larger better more easily larger r f lower lower r f higher table 4. affects of rc value figure 16. ocp regulati on with difference 5. pcb layout consideration 5.1 high frequency loop consideration as shown in figure 17, there are four major high frequency current loops: 1. the current path from bulk capacitor, transformer, mosfet, r cs returning to bulk capacitor 2. the path from gate pin, mosfet, r cs returning to the ground of ic 3. the rcd clamp circuit is a high frequency loop 4. transformer, rectifier diode, and output capacitor is also a high frequency current loop the loops must be as short as possible to decrease the radiate area for a better emi, and if the mosfet and schottky diode have heat sink, the heat sink should be connected to their ground separately. figure 17. high current loop in addition, the ic should not be placed in the loop of switching power trace, and in some applications, the power ground could be crossed over by the control signal (low current and low voltage), but the switching power trace with pulsating high voltage should not be crossed over. 5.2 esd consideration electro-static discharge (esd) is an important testing item for switching power supply. the system?s ability for bearing the test could be improved by designing a path to release the electric charge to the ground. as shown in figure 18, the red line represents the proposed path to release the charge. the copper tips for discharging should be placed between primary side and secondary side, but the distance between two copper tips should be consistent with the requirement of the safety specification . the input common mode filter and differential mode filter will affect the effect of transient discharging, so the copper tips should be added and their distance should be as short as possible. another way is placing a resistor paralleled with the inductor to replace the copper tip and the resistor?s value is about 1k ? to 5k ? . a smaller resistor is helpful to esd but has bad effects on lighting surge.
application note 1096 dec. 2012 rev. 1. 0 bcd semiconductor manufacturing limited 7 ac cx1 l1 c1 r3 r6 ntc r8 r7 r9 r11 r14 r15 c8 r16 r17 r load c9 c2 bd1 c3 c7 c6 l3 c4 d1 d2 d3 d4 t u1 u2 u3 l2 r1 r2 r5 r10 r13 f1 rt1 c5 r12 fb sense gate gnd ctrl 6 1 3 4 vcc 5 2 cy1 q1 ap3105nx figure 18. the path of release charge of esd 5.3 layout consideration for surge test figure 19 shows a circuit example which is under lightning surge test. the surge signal crosses between input line cable and secondary earth ground. possible surge current paths i1, i2 and i3 are shown in the diagram. i2 is the current which passes through ycap, and i3 is the current which passes through transformer from secondary gnd to primary aux winding gnd. i2 and i3 may interfere ic gnd if ycap gnd and aux gnd have a common trace with ic gnd on the layout. i1 is the current which passes through transformer from secondary gnd to primary bulk cap. i1 normally will not influence ic because there is a large resistor between ic pin and bulk cap terminal. a proper ?ground? layout is a so-called ?star? connection which is highly recommended for primary gnd layout. as shown in figure 19, the gnd of mosfet, auxiliary winding gnd, ycap gnd and control ic gnd are separated, and finally connected toge ther on bulk capacitor ground. the width of these grounds should be kept as large as possible. figure 19. ground layout for surge test immunity
application note 1096 dec. 2012 rev. 1. 0 bcd semiconductor manufacturing limited 8 6. demo design of 12v 2a adaptor 12v 2a demo using flyback topology is designed, and the system specification is shown as follows: ? output voltage and current: 12v/2a ? input voltage range: 90vac to 265vac table 5 shows the demo board components list. figure 20 shows the application circuit schematic. item type item type item type c2 102/1kv, ceramic d10 vf30100s, to220 r s1 , r s2 1.6 ? , 1206 c3 17 f/400v, al cap r1 9.1r, 1206 l4 220 h, 0510 c4 3.3 f, al cap r2 short u1 817c c5 680nf, 0603, ceramic r4 1k, 0603 u2 ap3105na, bcd c6 1000 f/16v, kzj r5 0.022r, 0805 u3 ap4320, bcd c7 17 f/400v, al cap r7 10 ? , 0805 t1 pq20, 1600 h c9, c13 2.2nf, 0805, ceramic r9 10k, 0603 q1 11n60, to220, infineon c10 1nf, 0603, ceramic r10, r14 5.6k, 0603 lf1 60 h, morota c11 33pf, 0603, ceramic r11 200k, 1206 fr 1a/250v c12 ycap, 102 r12 8.2k, 0603 vr1 varistor, 10k621 c20 2.2 f, 0603, ceramic r13 2.4k//18k, 0603 bridge1 kbp206 d1, d5 fr107, 0805 r15 220 ? , 0603 d2 1n4148, 0805 r18, r21 2.5m, 1206 table 5. bom of demo board (12v/2a) figure 20. application circuit schematic
application note 1096 dec. 2012 rev. 1. 0 bcd semiconductor manufacturing limited 9 table 6 shows the standby loss test result and table 7 sh ows the efficiency test result with no output cable. table 6. standby loss test result table 7. efficiency with pcb terminal v in 115v/50hz 150v/50hz 230v/50hz 264v/50hz p stb 42mw 46mw 63mw 83mw 0.5a 1a 1.5a 2a av 115v in 88.6% 88.7% 88.9% 88.3% 88.6% 230vi n 87.2% 88% 88.6% 88.2% 88%
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